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ASAHI KASEI
[AK2574]
AK2574
156M Laser Diode Driver + APC for Burst Mode
Features - 156M Laser Diode Driver for burst mode application - BIAS current switching - Programmable laser BIAS and modulation current controlled by an on-chip temperature sensor (APC_FF) - Two current output 8 bit DACs, I-DAC1: 85mA sink for modulation current I-DAC2: 54mA sink for BIAS current - Power failure alarm (TXACT), CLK failure alarm (CLKALM) - I2CTM compatible digital I/F - Duty adjustment - Single 3.3V +/- 0.2V operation Applications ITU-T G.983 ATM-PON ONU I2CTM is a trademark o f Philips Corporation. Description The AK2574 is a 1chip LDD (Laser Diode Driver) and an APC (Auto Power Control) for burst mode application such as ATM-PON. It contains not only 156M LDD for modulatin current but also BIAS current switching, programmable BIAS and modulation currents, duty adjustment, I2CTM interface, an EEPROM for storing LD characteristics and user information. The AK2574 has an APC FF (Feed-forward) function that supplies a programmed current in response to the temperature. All program and operational functions can be set through the I2CTM compatible interface and stored in the on-chip EEPROM. Ordering Information Product Number AK2574VB Block Diagram PKG BCC++ 48 (7mm * 7mm)
LD
SEL IMODN DATAP DATAN DATA (LVPECL) data FF data_ff AND DUTY_ ADJ MOD DRIVER IMOD IBIAS IBIASR1 IBIASC1 0.1uF IBIASC2 0.1uF BRSTP BRSTN BRST (LVPECL) brst FF brst_ff Ibias 330
BIAS DRIVER
CLKP CLKN
CLK (LVPECL)
clk
CLK_ DET
Imod
SEL Monitor PD i_pd PDIN CLKALM DAC (TXACT) txact_ref
COMP (TXACT)
comp_out
SET/ RESET
AND
TXACT
RPD TEMPMON TEMPSENS ADC APC_FF I-DAC2 OSC EEPROM BIAS_ GEN Digital I/F (I 2CTM) SCL SDA* WP** TXDIS I-DAC1
BIAS RB (12k)
CONTROL
*: Open Drain **: Pull-up

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ASAHI KASEI - Contents -
[AK2574]
. Pin Description 4 . Absolute Maximum Rating 6 . Recommend Operation Conditions 6 . Electrical Chracteristics 6 1. Power Consumption 6 2. EEPROM 6 3. Digital Input / Output DC Characteristics 7 4. I2CTM I/F AC Characteristics 7 5. LVPECL I/F 8 6. BRST Timing (SEL="L", without CLK) 8 7. BRST Timing (SEL="H", with CLK) 9 8. I-DAC1 9 9. I-DAC2 10 10. Duty Cycle Adjustment10 11. DAC (TXACT)10 12. PDIN Capacitance10 13. BIASGEN10 14. Temperature Sensor 10 15. ADC11 16. Power On Reset 11 17. On-chip Oscillator 11 . Package Information 12 . Circuit Description 13 1. Parameter Notation 13 1.1 Parameter Definition 13 1.2 Operation Overview13 2. LD Driver 14 2.1 Driver 14 2.2 LVPECL Input (DATAP/DATAN/CLKP/CLKN/BRSTP/BRSTN) 14 2.2.1 LVPECL Input Characteristics 14 2.2.2 Input Timing (SEL="H", in the case of the latched DATA with CLK) 15 2.2.3 Input Timing (SEL="L", in the case of direct DATA) 16 2.3 Duty Adjustment 16 2.4 APC 17 2.4.1 APC_FF17 2.4.2 I-DAC 17 2.4.3 I-DAC2 Minimum Current Output18 2.4.4 Temperature Sensor (TEMPSENS)18 3. Alarm 20 3.1 TXACT20 3.2 CLKALM 21 4. Shutdown 21 5. I2CTM I/F22 5.1 Memory Map 22 5.2 Read / Write Operation 23 5.2.1 Byte Write23 5.2.2 Page Write23 -22003/12
ASAHI KASEI
[AK2574]
5.2.3 Current Address Read23 5.2.4 Random Read23 5.2.5 Sequential Read23 5.2.6 Data Change24 5.2.7 Start / Stop Condition 24 5.3 EEPROM 24 5.4 Register 26 6. Operation Mode 27 6.1 Self-running Mode 27 6.2 Adjustment Mode 27 6.3 EEPROM Mode 27 6.4 MODE Control 27 6.5 Operation Mode Protection 27 6.6 Operation Mode Status 27 7. Module Adjustment Example28 . Circuit Example 29

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ASAHI KASEI
[AK2574]
. Pin Description The symbol of I/O column shows below. Ai: Analog input, Ai_l: LVPECL input, Ao: Analog output Di: Digital input, Di_pu: Digital input with pulled-up resistor, Do: Digital output, Dio_od: Digital input / output (open drain) PWR: Power or VSS PIN# Symbol 1 SDA 2 3 4 NC SCL CLKALM Function Serial data input / output (Open drain). Connect to VDD with 4.7k to 10k resistor. No Connection. Connect to the VSS (recommended) or leave open. Serial clock input. The data (SDA) is shifted in at the rising edge of SCL and is shifted out at the falling edge of SCL. Sets the alarm when detects 1's or 0's sequential clock input. During CLKALM detection, the AK2574 goes into "TX disable". The detection time is 100ns (typ). The CLKALM is reset when 1 clock is detected. The polarity can be set with EEPROM. When SEL="L", CLKALM is set "non-detected" polarity. TX Disable. The polarity can be set with EEPROM. When set "TX disable", IMOD and IBIAS are Hi-Z. Use 4.7k or more for externally pulled-up or pulled-down. Write Protect. Internally pulled-up with 20k (typ). "H" sets device address 101000 and only user area of EEPROM can be accessed as read-only. "L" sets device address as 1010 and full of EEPROM can be accessed as read/write. Negative LVPECL clock input. Input Impedance >= 10k. Connect to VSS when SEL = "L". Positive LVPECL clock input. Input Impedance >= 10k. Connect to VDD or leave open when SEL ="L". "H" for latched data with clock. DATA (DATAP - DATAN) and BRST (BRSTP - BRSTN) are shifted into the falling edge of CLK. (CLKP - CLKN). "L" for direct data. Negative LVPECL data input. Input Impedance >= 10k Positive LVPECL data input. InputImpedance >= 10k No Connection. Connect to the VSS or leave open. Test input. Leave open for normal operation. Negative LVPECL burst control input. Input Impedance >= 10k Positive LVPECL burst control input. Input Impedance >= 10k Test input. Connect to VSS for normal operation Test input. Connect to VSS for normal operation Test input. Connect to VSS for normal operation Test input. Connect to VSS for normal operation VSS for MOD driver circuit. Power supply for MOD driver circuit. Power supply for MOD current circuit. VSS for MOD current drive circuit. No Connection. Connect to the VSS (recommended) or leave open. -4I/O Dio_od Remark AC load 100pF Do not leave open AC load 30pF
Di Do
5
TXDIS
Di
Do not leave open
6
WP
Di_pu
7 8 9
CLKN CLKP SEL
Ai_l Ai_l Di Do not leave open
10 11 12, 13 14 15 16 17 18 19 20 21 22 23 24 25, 26
DATAN DATAP NC TEST6 BRSTN BRSTP TEST5 TEST4 TEST3 TEST2 VSSDR VDDDR VDDMD VSSMD NC
Ai_l Ai_l Do Ai_l Ai_l Di Di Di Di PWR PWR PWR PWR Connect to VSS. Leave open

2003/12
ASAHI KASEI Pin Description (Continued) PIN# Symbol Function 27, 28 IMODN Negative MOD current output. Sinks MOD current when input data is "L". 29, 30 IMOD Positive MOD current output. Sinks up to 85mA (typ) MOD current when input data is "H". MOD current is adjusted with I-DAC1. IMOD voltage should be (VDD - 1.8V) or more. 31 VSSMD VSS for MOD current drive circuit. 32 VSSBI VSS for BIAS current drive circuit. 33, 34 IBIAS BIAS current output. Sinks up to 54mA (typ) current. BIAS current is adjusted with I-DAC2. IBIAS voltage should be (VDD - 1.8V) or more. 35 VSSBI VSS for BIAS current drive circuit. 36 IBIASC1 Connect to VSS with 0.1uF 50% (in the operating temerature range) capacitor. 37 NC No Connection. Connect to the VSS (recommended) or leave open. 38 IBIASC2 Connect to VSS with 0.1uF 50% (in the operating temerature range) capacitor. 39 IBIASR1 Connect to IBIASSC1 with 330 1% resistor. 40 PDIN Monitor PD voltage input. Monitor PD current is converted to the voltage with resistor. TEMPMON Temperature sensor monitor output. 41
[AK2574]
I/O Ao Ao
Remark
PWR PWR Ao PWR Ao
Ao Ao Ai Ao AC load 30pF DC load 50k
42 43 44 45
BIAS AVDD AVSS TXACT
46 47 48
TEST1 DVSS DVDD
BIAS reference for internal circuit. Connect to VSS with 12k 1% resistor. Power supply for analog circuit. VSS for analog circuit. TXACT is set when PDIN voltage beyond the reference voltage (DACAPC output) and is kept during BRST="H". TXACT is reset when BRST is transient "H" "L". The polarity can be set with EEPROM. TXACT is valid within 2ms after power-up. Test input. Connect to VSS for normal operation VSS for digital circuit. Power supply for digital circuit.
Ao PWR PWR Do
Di PWR PWR
Connect to VSS.
Center PAD of PKG should be connected to the VSS for good electrical performance and radiation of heat.

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ASAHI KASEI . Absolute Maximum Rating Item Symbol Min Max Unit Supply Voltage VDD -0.3 6.0 V GND VSS 0.0 0.0 V Input voltage VIN VSS - 0.3 VDD + 0.3 V Input Current IIN -10 10 mA Storage Temperature TSTG -55 130 C Stress beyond "Absolute Maximum Range" may cause permanent damage to the device. Note 1: Except Data retention. Data retention is prescribed at section- 2. EEPROM. . Recommended Operation Conditions Item Operating Ambient Power Supply Symbol Ta1 VDD1 VDD2 VSS Min -40 3.1 3.0 0.0 Typ 3.3 3.3 0.0 Max 85 3.5 3.5 0.0 Unit C V V V
[AK2574]
Remarks Reference Voltage Except VDD Except VDD Note 1
Remarks Except AVDD AVDD ReferenceVoltage
. Electrical Characteristics 1. Power Consumption Item Symbol min typ max Unit Remarks Supply Current 1 (All VDD) IDD1 8.5 11 mA Note 1, 2, 4 Supply Current 2 (All VDD) IDD2 36 41 mA Note 1, 3, 5 Supply Current 3 (AVDD only) IDD3 10.1 12.5 mA Note 1, 3, 5 Note 1: without BIAS and modulation current. Note 2: R_DAC1 = R_DAC2 = 00h, PDIN = 1V. Note 3: R_DAC1 = R_DAC2 = FFh (Full code), PDIN = 1V. Note 4: DATAP = BRSTP = "L", DATAN = BRSTP = "H", CLKP = "H", CLKN = "L". Note 5: 155.52Mbps, PN7, BRSTP="H", BRSTN="L". 2. EEPROM Item Endurance Data retention
Min 10000 10
max -
Unit Remarks Write Cycle Note 1 Year Junction Temperature = 85
Note 1: This parameter is characterized and is not 100% tested. Important Notice: The AKM factory adjusted data are stored in advance at address location (Device Address = A6h, Address = 60h) for the offset of the on-chip temperature sensor. If such excess temperature stress is to be applied to the AK2574 which exceeds a guaranteed EEPROM data retention conditions (for 10 years at 85), it is important to read the pre-determined value inadvance and to re-write the same data back into EEPROM after an exposure to the excess temperature environment. Even if the exposure time is shorter than the retention time, any accelerated temperature stress tests (such as baking) are performed, it is recommended to read the pre-set data first and to re-write it after the test. Access to un-used address locations is not functionally guaranteed. Refer to section- 5.3 for EEPROM map.

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ASAHI KASEI 3. Digital Input / Output DC Characteristics Item Symbol min Input High Level VIH 2.0 Input Low Level VIL Output High Level VOH 0.9VDD Output Low Level VOL
[AK2574]
max 0.8 0.4
Unit V V V V
Conditions Note 1 IOH = -0.2mA IOL = 1mA (SDA) IOL = 0.2mA (Except SDA) except WP pin WP pin
Input Leakage Current 1 IL1 10 uA Input Leakage Current 2 IL2 350 uA Note 1: except DATAP, DATAN, CLKP, CLKN, BRSTP and BRSTN pins.
4.
I2CTM I/F AC Characteristics Symbol Parameter min tSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 4.7 tHigh Clock Pulse Width High 4.0 tI Noise Suppression Time tAA Clock Low to Data Out Valid 0.1 tBUF Time Before a New Transmission 4.7 tHD.STA Start Hold Time 4.7 tSU.STA Start Setup Time 4.0 tHD.DAT Data Hold Time 0 tSU.DAT Data Setup Time 200 tR Input Rise Time tF Input Fall Time tSU.STO Stop Setup Time 4.7 tDH SDATA Hold Time 100 tWR Write Cycle Time Note 1: This parameter is characterized and is not 100% tested.
tF
max 100
100 4.5
1.0 0.3
10
Unit kHz us us ns us us us us us ns us us us ns ms
Remark
Note 1 Note 1
tR
SCL tSU.STA tHD.STA tHD.DAT tSU.STO
tSU.DAT
SDA (IN) tBUF tAA tDH
SDA (OUT)

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ASAHI KASEI 5. LVPECL I/F (CLKP, CLKN, DATAP, DATAN, BRSTP, BRSTN) Item Symbol min typ Single-ended Input Voltage Swing Vamp 0.1 Common Voltage Vcom 0.5*VDD BIAS Voltage Vbias 0.6*VDD Input Impedance Zin 10
Vamp Vcom CLKP/CLKN DATAP/DATAN BRSTP/BRTSTN
[AK2574]
max 1.2 VDD - 1.0
Unit V V V k
Remarks
BRST Timing (SEL="L", without CLK) Item Symbol Conditions min typ max Unit Remarks 12.8 ns Delay Time of BRST "L" "H" Tdr-bd to First DATA Delay Time of Last DATA Tdf-di Last Data=1 2 ns to IBIAS OFF R_DAC2=0Fh IBIAS Overshoot rib1 R_DAC2=0Fh 120 150 % Note 1 R_DAC2=2Fh 108 % R_DAC2=FFh 98 % IBIAS Error before 2ns rib2 R_DAC2=0Fh +/- 15 % Note 1 of First DATA Tdf-bt R_DAC2=0Fh 16 ns Delay Time of BRST "H""L" to TXACT OFF Delay Time of First DATA Tdr-dt Note 2 to TXACT Detection Note 1: This parameter is characterized and is not 100% tested. Note 2: Depends on TXACT detection level, Monitor PD current, etc. For more information, see "VI. 3.1 TXACT". 6.
BRSTP - BRSTN
Tdr-bd DATAP - DATAN
100% Nominal IBIAS Current rib1 rib2
2ns IMOD Current Tdf-bt Tdr-dt TXACT
Tdf-di

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ASAHI KASEI
[AK2574]
7. BRST Timing (SEL="H", with CLK) Item Symbol Conditions min typ max Unit Remarks DATA Set-up Time Tsu 1.5 Note 1 DATA Hold Time Th 1.0 BRST Set-up Time Tsu-b 1.5 BRST Hold Time Th-b 1.0 12.8 12.86 ns Delay Time of BRST "L" "H" Tdr-bd to First DATA Delay Time of Last DATA Tdf-di Last Data=1 2 ns to IBIAS OFF R_DAC2=0Fh IBIAS Overshoot rib1 R_DAC2=0Fh 120 150 % Note 1 R_DAC2=2Fh 108 % R_DAC2=FFh 98 % IBIAS Error before 2ns rib2 R_DAC2=0Fh +/- 15 % Note 1 of First DATA 16 ns Tdf-bt R_DAC2=0Fh Delay Time of BRST "H""L" to TXACT OFF Delay Time of First DATA Tdr-dt Note 2 to TXACT Detection Note 1: This parameter is characterized and is not 100% tested. Note 2: Depends on TXACT detection level, Monitor PD current, etc. For more information, see "VI. 3.1 TXACT".
Th-b BRSTP - BRSTN Tsu-b Tdr-bd
CLKP- CLKN Tsu Th
DATAP - DATAN
100% Nominal IBIAS Current rib1 rib2
2ns
Tdf-di
IMOD Current Tdf-bt Tdr-dt TXACT
8. I-DAC1 Item Condition Resolution Output Current with IMOD = VDD - 1.8V Full Code Current Supply with IMOD = VDD Shutdown 1 LSB Current Step IMOD = VDD - 1.8V DNL IMOD = VDD - 1.8V
min 76
typ 8 85
max 94 100
Unit Remark bit mA uA mA LSB TXDIS = "1"
0.333 -1 +1
Code 20h to FFh

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ASAHI KASEI 9. I-DAC2 Item Condition Resolution Maximum Output IBIAS = VDD - 1.8V Current R_DAC2=FFh Minimum Output IBIAS = VDD Current 1 1 R_DAC2 5 Minimum Output IBIAS = VDD Current 2 R_DAC2 = 0 IBIAS = VDD Current Supply with Shutdown 1 LSB Current Step IBIAS = VDD - 1.8V DNL IBIAS = VDD - 1.8V 10. Duty Cycle Adjustment Item Maximum Pulse Extended 1 LSB Pulse Extended Step Pulse Extended Stability
[AK2574]
min 48
typ 8 54 1.06 0
max 60 1.2
Unit Remark bit mA mA mA R_DAC2 = 1 to 5 R_DAC2 = 0 TXDIS = "1"
100 0.212 -1 +1
uA mA LSB
Code 20h to FFh
Condition
min 0.5
typ 0.03
max
0.3ns Extended Ta=-40 to 85, VDD=3.13.5V Note 1: This parameter is characterized and is not 100% tested. 11. DAC (TXACT) Item Resolution Output Voltage
0.2
Unit ns ns ns
Remarks Note 1 32 Steps Note 1
Condition R_CMPTH[2:0]=011 R_CMPTH[2:0]=010 R_CMPTH[2:0]=001 R_CMPTH[2:0]=000 R_CMPTH[2:0]=100 R_CMPTH[2:0]=101 R_CMPTH[2:0]=110 R_CMPTH[2:0]=111
min 0.86 0.76 0.66 0.56 0.46 0.36 0.26 0.16
typ 3 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2
max 0.94 0.84 0.74 0.64 0.54 0.44 0.34 0.24
Unit bit V V V V V V V V
Remarks
12. PDIN Capacitance Item PDIN Capacitance 13. BIASGEN Item BIAS pin Voltage
Condition
min
typ 14
max 26
Unit pF
Remarks
Condition
min
typ 1.2
max
Unit V
Remark
14. Temperature Sensor Item Condition min Voltage Slope TEMPMON Voltage -12.14 Offset Adjustment Target Ta = 35 Note 1: This parameter is characterized and is not 100% tested.
typ -11.56 1.215
max -10.98
Unit mV / V
Remark Note 1

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ASAHI KASEI 15. ADC Item Resolution Maximum Input Voltage Minimum Input Voltage DNL
[AK2574]
Condition
min 2.09 -1/2
typ 7 2.2 0
max 2.31 +1/2
Unit bit V V LSB
Remark
16. Power On Reset Item Condition min typ Detect Voltage 2.3 2.5 When detects the voltage drop, the AK2574 goes into shutdown condition. 17. On-chip Oscillator Item Clock Frequency
max 2.7
Unit V
Remark
Condition
min
typ 2.15
max
Unit MHz
Remark

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ASAHI KASEI . Package Information (1) Package Type: 48 pin BCC++ (2) Marking Information: (a) PIN#1 Indication: (b) Logo: AKM (c) Marking Code: AK2574VB (d) Date Code: YYWWXXX (7 digit)
[AK2574]
AKM AK2574VB YYWWXXX
(3) Package Outline
6.2 7.00.1 37 25 0.5 0.50.1 25 37
0.09MIN
5.1 5.50.06 7.00.1 6.15
"B" 0.450.06 0.450.06
6.2
"A"
1
13
"C"
13 5.0 6.15
1
"A" Part
"B" Part 0.40.06 0.450.06
"C" Part
0.80 MAX
0.05
0.0750.025
0.14 MIN
C0.2
0.30.06
0.450.06

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ASAHI KASEI . Circuit Description
[AK2574]
1. Parameter Notation 1.1 Parameter Definition In the AK2574 Circuit Description, in order to distinguish various pre-set parameter sources from EEPROM, Registers or Device pins, "Identifier - Main name" notation is used as shown in Table 1-1. For ease of operational description, small letters sometimes expresses internal signals. Table 1-1 Parameter Definitions Identifier Register R_ EEPROM Ether or both Register or /and EEPROM PIN BLOCK Internal Node E_ RE_ P_ None None Main Name REGISTER name (All Capital) EEPROM name (All Capital)) REGISTER / EEPROM name (All Capital) PIN name (All Capital) BLOCK name (All Capital)) signal name (small letter) Remark Indicates register Indicates EEPROM Example R_DAC1 E_DAC1
Indicates either register RE_DAC1 or EEPROM P_PDIN I-DAC1 txact_ref
1.2 Operation Overview The AK2574 has 3 primary functions; 125M / 156M modulation (MOD) current switching and BIAS current switching part, APC (Automatic Power Control) part, and the Control part to control operation modes of the AK2574 operation. There are 3 operation modes in the AK2574. Since each adjusting function is controlled through I2CTM Interface, it realizes an automatic parameter adjustment. (1) Self-running Mode Self-running mode is ready for normal operation after all adjustments are completed. In this mode, temperature detection, EEPROM access and feeding current are automatically performed using the on-chip oscillator. The AK2574 works in this mode after power-on. (2) Adjustment Mode Adjustment mode is designed for training the LD characteristics. The AK2574 operates according to the register settings set through the I2CTM I/F. (3) EEPROM Mode EEPROM mode is used for storing LD characteristics into EEPROM via I2CTM I/F.

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ASAHI KASEI
[AK2574]
2. LD Driver Fig 2-1 illustrates the block diagram of LD driver function. The AK2574 LD driver contains a Driver part, an APC part, a LVPECL I/F part and a programmable duty adjustment. The driver part is composed of 156M MOD current switching controlled by DATA, and BIAS current switching controlled by BRST. APC part is composed of a programmable BIAS and MOD currents in response to the temperature (APC_FF), an on-chip temperature sensor, and 2 current DACS (I-DAC1 and I-DAC2). The LVPECL I/F part is composed of LVPECL I/F for data, clock and the burst control signal (BRST). Fig 2-1 Driver Block Diagram
LD SEL IMODN DATAP DATAN DATA (LVPECL) data FF data_ff AND DUTY_ ADJ IMOD IBIAS IBIASR1 IBIASC1 0.1uF 330
CLKP CLKN
CLK (LVPECL)
clk SEL
CLKALM Driver
IBIASC2
0.1uF BRSTP BRSTN BRST (LVPECL) brst FF LVPECL I/F APC vtemp R_TEMP Imod I-DAC1 brst_ff
R_DAC1 ADC EEPEOM R_DAC2
TEMP_SENS
Ibias I-DAC2
2.1 Driver The 156M MOD driver iscomposed of the differential current switches, and it sinks the MOD current from IMOD pin when DATA (DATAP - DATAN) = 1 and sinks the current from IMODN when DATA = 0. DATA is set "0" when BRST (BRSTP - BRSTN) = 0. The BIAS driver is composed of the single-end current switch, and it sinks the BIAS current from IBIAS when BRTS=1. To protect the last LD current at BRST 10, BIAS current turned off timing is delayed for a duty extended when the last DATA=1. 2.2 LVPECL I/F (DATAP, DATAN, CLKP, CLKN, BRSTP, BRTSN) The AK2574 supports direct data or latched data input (see Table 2 Connect CLKP = VDD or leave open and -1). CLKN = VSS when SEL = "L". Table 2-1 Data input SEL (CMOS) "L" "H"
Direct data Latched data with clock
2.2.1 LVPECL Input Characteristics Table 2-2 shows LVPECL input characteristics. The AK2574 LVPECL input, which is biased to 0.6 * VDD with 10k or more impedance respectively.

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ASAHI KASEI Table 2-2 LVPEL Interface characteristics Item Symbol min typ Single-ended Input |Vamp| 0.1 Voltage Swing Common Voltage Vcom 0.5*VDD BIAS Voltage Vbias 0.6*VDD Input Impedance Zin 10 Set-up Time tsu 1.5 Hold Time th 1.0 Note 1: This parameter is characterized and is not 100% tested. Fig 2-2 DATA / CLK / BRST Input Level
Vamp Vcom CLKP/CLKN DATAP/DATAN BRSTP/BRTSTN
[AK2574]
max 1.2 VDD - 1.0
Unit V V V k ns ns
Reference Fig 2-2 Fig 2-2 Fig 2-3 Fig 2-3 Fig 2-4 Fig 2-4
Remarks
Note 1
Fig 2-3 LVPECL input circuit
AK2574
130
Zin
82
DATAP DATAN CLKP CLKN BRSTP BRSTN
Vbias
Fig 2-4 Set-up & Hold Time
DATA (DATAP - DATAN) tsu CLK (CLKP - CLKN) th
2.2.2 Input Timing (SEL="H", in the case of the latched DATA with CLK) BRST (BRSTP - BRSTN) and DATA (DATAP - DATAN) are shifted into AK2574 at the falling edge of CLK (CLKP - CLKN). BIAS driver is turned on within 2 clock (12.8ns max) when BRST = 1. DATA input should be 2 clock (= 12.8ns min) behind BRST = 1. Fig 2-5 illustrates the timing example.

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ASAHI KASEI Fig 2-5 Input timing example with CLK
BRSTP - BRSTN
[AK2574]
CLKP- CLKN Preamble + Delimiter (24bit include Guard Time)
ATM Cell (53byte)
DATAP - DATAN
2 CLK (typ)
2.2.3 Input Timing (SEL="L", in the case of direct DATA) AK2574 operates without CLK when SEL="L". DATA input should be 12.8ns or more behind BRST = 0 1 transition. To protect the last DATA, BRST 1 0 transition should be behind the last DATA input. Fig 2-6 illustrates the timing example. Fig 2-6 Input timing example without CLK
BRSTP - BRSTN
12.8ns (min) DATAP - DATAN
Preamble + Delimiter (24bit included Guard Time)
ATM Cell (53byte)
2.3 Duty Adjustment AK2574 supplies a programmed duty adjustment in response to the temperature from an on-chip temperature sensor (every 6, Duty data is stored in E_DUTY_TC, see Table 6-3 for more information). Write same data into E_DUTY_TC for constant duty adjustment. Table 2 and 2-4 show the characteristics of duty adjustment function. -3 Table 2-3 Duty Adjustment characteristics Item Symbol min Maximum Pulse Extended Td 0.5 1 LSB Pulse Extended Step Tstep Pulse Extended Stability Tsta typ 0.03 0.2 max Unit ns ns ns Remarks Note 1 32 Steps Ta=-40 to 85, VDDDR=3.13.5V 0.3ns Extended (Note 1)
Note 1: This parameter is characterized and is not 100% tested. Table 2-4 Pulse Extended R_DUTY Pulse Extended (typ) [ns] 0 0 1 0.03 2 0.06 . . . . 30 0.90 31 0.93 Remark

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ASAHI KASEI
[AK2574]
2.4 APC AK2574 provides the APC (Auto Power Control) function for the burst mode application. APC is composed of a programmable BIAS and MOD currents in response to the temperature (APC_FF), an on-chip temperature sensor, and 2 current DACs (I-DAC1 and I-DAC2). 2.4.1 APC_FF Fig 2-7 illustrates the APC_FF functions. The operation is as follows: (1) Analog to digital conversion of the voltage (7 bit) that reflects the temperature for every temperature detection period (128ms typ). (2) Read the 8 bit current data (address is indicated by the ADC data) from EEPROM and set this value to the I-DACs. If the current data over temperature is set to each EEPROM address, the compensated current is supplied to the LD automatically. To use this function, current data should be stored in EEPROM in advance. The temperature sensor covers -40 to +115 and EEPROM is prepared with 1.5 steps. Fig 2-7 APC FF function
TEMPSENS ADC (7bit) R_TEMP EEPROM R_DAC1 I-DAC1 MOD Driver MOD Current Addressing with R_TEMP Address Data R_DAC2 Memory for I-DAC1 Temperature LD
TEMPSENS charatcteristics Voltage
I-DAC2
BIAS Driver BIAS Current
Memory for I-DAC2
2.4.2 I-DAC AK2574 has two current output 8 bit DACs; I-DAC1 and I-DAC2. I-DAC1 is 85mA @ Full code sink type current DAC for MOD current and I-DAC2 is 54mA @ Full code sink type current DAC for BIAS current. Table 2-5 shows I-DAC1 characteristics and Table 2-6 shows I-DAC2 characteristics. Table 2-5 I-DAC1 Characteristics Item Condition Resolution Output Current with IMOD = VDD - 1.8V Full Code 1 LSB Current Step IMOD = VDD - 1.8V DNL IMOD = VDD - 1.8V min 76 typ 8 85 0.333 -1 +1 max 94 Unit Remark bit mA mA LSB
Code 20h to FFh

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2003/12
ASAHI KASEI Table 2-6 I-DAC2 Characteristics Item Condition Resolution Maximum Output IBIAS = VDD - 1.8V R_DAC2=FFh Current Minimum Output IBIAS = VDD Current 1 1 R_DAC2 5 Minimum Output IBIAS = VDD Current 2 R_DAC2 = 0 1 LSB Current Step IBIAS = VDD - 1.8V DNL IBIAS = VDD - 1.8V
[AK2574]
min 48
typ 8 54 1.06 0 0.212
max 60 1.2
Unit Remark bit mA mA mA mA LSB See 2.4.3
-1
+1
Code 20h to FFh
2.4.3 I-DAC2 Minimum CurrentOutput Table 2-7 shows the relationship between EEPROM setting (E_DAC2_TC) and I-DAC2 code (R_DAC2). The data to be set to I-DAC2 (R_DAC2) is limited to 5 or more for BIAS current circuit stability. From 1 to 5 code is changed to 5 and is set to I-DAC2. In the case of 0 code, BIAS driver is turned off and IBIAS pin is Hi-Z. Table 2-7 I-DAC2 Code Setting E_DAC2_TC R_DAC2 (I-DAC2 code) 0 BIAS Driver = OFF 5 14 5 or more E_DAC2_TC Remarks IBIAS = Hi-Z Code 1 to 4 is forced to be 5 No modification
2.4.4 Temperature Sensor (TEMPSENS) Fig 2-8 shows an on-chip temperature sensor characteristics and Table 2-8 shows the relationship between detected temperature and ADC code. Fig 2-8 On-chip Temperature Sensor Characteristics
On-chip Temperature sensor characteristics 2.5
2.0 Output voltage V [V]
1.5
1.0
0.5
0.0 -40 -20 0 20 40 60 80 100 120 Temperature t [C]
(1) (2) (3) (4)
Slope: -11.56mV/ (typ) V(t) = -0.01156 * t + 1.62 [V] (typ) AD_code = int( V(t) / 2.2 * 127 +0.5) = int(-0.667*t + 94.0) Temperature step @ AD_code=1LSB: 1.49/LSB
Note: Temperature sensor detects the junction temperature, not LD or ambient temperature. -182003/12
ASAHI KASEI Table 2-8 AD code and detected temperature [typ] AD code AD code Temp [] Temp [] 0 140.1 32 92.2 1 138.6 33 90.7 2 137.1 34 89.2 3 135.6 35 87.7 4 134.1 36 86.2 5 132.6 37 84.7 6 131.1 38 83.2 7 129.6 39 81.7 8 128.2 40 80.2 9 126.7 41 78.7 10 125.2 42 77.2 11 123.7 43 75.7 12 122.2 44 74.2 13 120.7 45 72.7 14 119.2 46 71.2 15 117.7 47 69.7 16 116.2 48 68.2 17 114.7 49 66.7 18 113.2 50 65.2 19 111.7 51 63.7 20 110.2 52 62.2 21 108.7 53 60.7 22 107.2 54 59.2 23 105.7 55 57.7 24 104.2 56 56.2 25 102.7 57 54.7 26 101.2 58 53.2 27 99.7 59 51.7 28 98.2 60 50.2 29 96.7 61 48.7 30 95.2 62 47.2 31 93.7 63 45.7
[AK2574]
AD code 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
Temp [] 44.2 42.7 41.2 39.7 38.2 36.7 35.2 33.7 32.2 30.7 29.2 27.7 26.3 24.8 23.3 21.8 20.3 18.8 17.3 15.8 14.3 12.8 11.3 9.8 8.3 6.8 5.3 3.8 2.3 0.8 -0.7 -2.2
AD code 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Temp [] -3.7 -5.2 -6.7 -8.2 -9.7 -11.2 -12.7 -14.2 -15.7 -17.2 -18.7 -20.2 -21.7 -23.2 -24.7 -26.2 -27.7 -29.2 -30.7 -32.2 -33.7 -35.2 -36.7 -38.2 -39.7 -41.2 -42.7 -44.2 -45.7 -47.2 -48.7 -50.2

-19-
2003/12
ASAHI KASEI 3. Alarm AK2574 has 2 alarm functions as shown in Table 3-1. Table 3-1 Alarm function ALM Detection condition TXACT When the PDIN voltage (monitor PD current) is beyond the reference voltage (txact_ref). TXACT is kept once TXACT detection until BRST="L". CLKALM When the detected 0s or 1s sequential CLK input (100ns typical). When detected CLKALM, AK2574 goes into "Shutdwon". Release condition BRST="L"
[AK2574]
Detected Time Depens on the condition. See "3.1 TXACT" for more information Polarity of CLK is 100ns (typ) changed 200ns (max)
3.1 TXACT Fig 3-1illustrates TXACT block diagram. TXACT is detected when the PDIN voltage is beyond the reference voltage (txact_ref), and TXACT is held during BRST = "H". The txact_ref is set with RE_DAC_TXACT. TXACT detection time depends on the Monitor PD current (i_pd) and capacitance (CMPD), external resistor (RPD), AK2574 PDIN capactance (CPDIN) and txact_ref voltage (see Fig 3-2 for the reference). Table 3-2 shows the PDIN capacitance (CPDIN) and Table 3-3 shouws the relationship between txact_ref and RE_DAC_TXACT. The polarity of TXACT can be set by RE_TXACT_POL (0: "H" at detection, 1:"L" at detection). The TXACT detection time (t_act) is estimated under the 50% mark data input and average monitor current as follows:
t _ act = - RPD * (CMPD + CPDIN ) * LN (1 -
txact _ ref ) RPD * i _ pd / 2
Note: TXACT detection time varies with input data pattern. Fig 3-1 TXACT block diagram
Monitor PD i_pd PDIN COMP txact_ref BRST SET/ RESET AND TXACT
RPD
CPDIN
DAC (TXACT)
comp_out
Fig 3-2 Reference figures for TXACT detection time
i_pd @ DATA=1 0 @ DATA=0 vpd COMP RPD CMPD CPDIN txact_ref
i_pd
comp_out

-20-
2003/12
ASAHI KASEI Table 3-2 PDIN capacitance (CPDIN) Item min PDIN Capacitance (CPDIN) Table 3-3 TXACT Reference Voltage RE_DAC_TXACT min 011 0.86 010 0.76 001 0.66 000 0.56 100 0.46 101 0.36 110 0.26 111 0.16
[AK2574]
typ 14
max 26
Unit pF
Remark
txact_ref typ max 0.9 0.94 0.8 0.84 0.7 0.74 0.6 0.64 0.5 0.54 0.4 0.44 0.3 0.34 0.2 0.24
Remarks unit V V V V V V V V
3.2 CLKALM CLKALM is detected when input CLK is 0's or 1's fixed more than 100ns (typ). The polarity of CLKALM can be set by RE_CLKALM_POL (0: "H" at detection, 1: "L" at detection). AK2574 goes into "shutdown" (see 4. Shutdown) when CLKALM is detected.
4. Shutdown Table 4-1 shows the shutdown condition and Table 4-2 shows AK2574 operation at shutdown. AK2574 goes into "Shutdown" when TXDIS request from TXDIS pin or CLKALM detection. The polarity of TXDIS can be set by RE_TXDIS_POL (0: "H" shutdown, 1: "L" shutdown). Table 4-1 Shutdown Condition TXDIS (Note1) CLKALM (Note2) Operation 1 X Shutdown 0 0 Normal Operation 0 1 Shutdown Note 1: 1 means shutdown request from TXDIS pin. Note 2: 1 means CLKALM detection. Table 4-2 AK2574 operation at shutdown Function Operation I-DAC1 / 2 output High-Z (0mA output) APC_FF Normal Operation MOD Driver DATA=0 BIAS Driver OFF (BRST=0) CLKALM Normal Operation TXACT Hold non-detected polarity Remarks Shutdown by pin Shutdown by CLKALM detection
Remarks

-21-
2003/12
ASAHI KASEI
[AK2574]
5. I2CTM I/F 5.1 Memory Map Table 5-1 shows the EEPROM / Register address map. Accessto memory (EEPROM / registers) is done via the I2CTM I/F format. WP (Write Protect) may limit the access of memory as shown in Table 5-2. Table 5-1 Memory map Device Address Device Address-1 A0h 1010 A0h A2h A4h A6h A6h A8h A8h A8h 1010 1010 1010 1010 1010 1010 1010 1010 Device Address-2 000 000 001 010 011 011 100 100 100 Address 00000000 to 01111111 10000000 to 11111111 00000000 to 11111111 00000000 to 11111111 00000000 to 01111111 10000000 to 11111111 00000000 to 00010011 00010011 to 11111110 11111111 Data User Area (EEPROM, 1kbit) No memory No memory Adjustment data (EEPROM, 3kbit) No memory Registers No memory AK2574 Operation mode change
Table 5-2 Memory access limitation with WP Item WP = "L" Device Address 1010xxx ACK (Note 1) when receive device address EEPROM / Register Full access Access Operating mode Full Page Write 16 byte (without registers) Sequential Read from 00000000000 to 01111111111 Registers Access Random access only Note 1: During EEPROM Write operation, no ACK is generated.
WP = "H" 1010000 when receive device address User area only (read only) Self running mode only from 00000000 to 01111111 -

-22-
2003/12
ASAHI KASEI 5.2 Read/Write Operation 5.2.1 Byte Write
SDA
S T A R T
[AK2574]
1010
Device Address-1
00
Device R/ Address-2 W A C K Address (MSB First)
0
A C K Data (MSB First)
0
AS CT KO P
5.2.2 Page Write AK2574 is capable of 16-byte page write.
SDA
S T A R T
1010
Device Address-1
00
Device R/ Address-2 W A C K Address (MSB First)
0
A C K Data (Address)
0
A C K Data (Address + 1)
0
A C K
....
0
A C K Data (Address + n)
0
AS CT KO P
5.2.3 Current Address Read The internal address counter maintains the last address accessed during the last read or write operation, incremented by one. The roll over address is changed WP setting. Refer to Table 5-2 in detail.
SDA
S T A R T
1010
Device Address-1
10
Device R/ Address-2 W A C K Data (MSB First)
1
N O A C K S T O P
5.2.4 Random Read A random read requires a "dummy" byte write sequence to specified "Address". After receive the ACK from AK2574, perform "current address read" (see 5.2.2).
SDA
S T A R T
1010
Device Address-1
00
Device R/ Address-2 W A C K
*1
Address (MSB First)
0
A C K S T A R T
1010
Device Address-1
10
Device R/ A Address-2 W C K Data (MSB First)
1
NS OT AO CP K
Dummy Write
*1: Don't care when WP="H"
5.2.5 Sequential Read Sequential read can be initiated as ether"Current Address Read" or "Random Read". After issuing either of them, the AK2574 continues to output data for each ACK received.
SDA
....
10
Device R/ A Address-2 W C K Data-1 (MSB First)
0
A C K Data-2
0
A C K
....
0
A C K Data-n
1
NS OT AO CP K

-23-
2003/12
ASAHI KASEI
[AK2574]
5.2.6 Data Change The SDA pin is normally pulled high with 4.7k to 10k. Data on the SDA pin may change only during SCL low time period. Data changes during SCL high periods will indicate a start or stop condition.
SCL
SDA
Data Stable Data Change
5.2.7 Start / Stop Condition Start Condition: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command. Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition.
SCL
SDA
START STOP
5.3 EEPROM EEPROM memory map is shown in Table 5-3, 5-4 and 5-5. EEPROM access islimited with WP pin and Operation mode (refer to Table 6-1, for more information). WP = "L": Full access WP = "H": User area only with read only (Note) The AKM factory adjusted data are stored in advance at address (Device Address = A6h, Address = 60h) for the offset of the on-chip temperature sensor. If such excess temperature stress is to be applied to this device which exceeds a guaranteed EEPROM data retention conditions ( for 10 years at 85), it is important to read the pre-determined value in advance and to re-write the same data back into EEPROM after an exposure to the excess temperature environment. Even if the exposure time is shorter than the retention time, any accelerated temperature stress tests (such as baking) are performed, it is recommended to read the pre-set data first and to re-write it after the tests.

-24-
2003/12
ASAHI KASEI Table 5-3 EEPROM Address MAP Device Address DATA (D7-D0) Address A0h User Area 00h (0) (1kbit) 7Fh (127) A0h 80h (128) No Memory FFh (255) A2h 00h (0) FFh (255) A4h E_DAC1_TC 00 h(0) Temperature data for I-DAC1 (1kbit) 7F h(127) A4h 80h (128) E_DAC2_TC Temperature data for I-DAC2 (1kbit) FFh (255) A6h E_DUTY_TC (256bit) 00h (0) Temperature data for Duty Adjustment 1Fh(31) A6h Reserved 20h (32) 5Fh (95) A6h Adjustment data 60h (96) (256bit) 7Fh (255) Table 5-4 Adjustment Data Area (Device Address = A6h) Address Function EEPROM E_VREFTRIM[7:4] E_TEMP_OFFSET [3:0] E_TXDIS_POL[2] E_TXACT_POL[1] E_CLKALM_POL[0] E_DAC_TXACT E_AKM_SET[1:0] 60h 60h 61h 61h 61h 62h 6Dh Oscillator Frequency Temperature sensor offset TXDIS Polarity TXACT Polarity CLKALM Polarity TXACT Reference Voltage AKM
[AK2574]
Initial Value 00h
Remark
00h 00h 00h 00h
Addressing with R_TEMP (1.5 step) Addressing with R_TEMP (1.5 step) Addressing with MSB 5bit of R_TEMP (6 step)
see Table 5-4 and 5-5
Bit 4 4 1 1 1 3 2
Initial Value Factory Setting 0 0 0 000 00
Remark
0: Shutdown at "H" 1: Shutdown at "L" 0: "H" at TXACT detection 1: "L" at TXACT detection 0: "H" at CLKALM detection 1: "L" at CLKALM detection see Table 3-2
Table 5-5 EEPROM Map (Adjustment Data Area) Address D7 D6 D5 D4 60h VREFTRIM 61h 62h 63h-6Ch 6Dh 6Eh-FFh
D3
D2 D1 D0 TEMP_OFFSET TXDIS_ TXACT_ CLKALM_ POL POL POL DAC_TXACT AKM_SET
Reserved

-25-
2003/12
ASAHI KASEI
[AK2574]
5.4 Register Register memory map is shown in Table 5-6 and 5-7. Register access is limited with WP pin and Operation mode (refer to Fig 6-1, for more information). Table 5-6 Register (Device Address = A8h) Register Address Function R_VREFTRIM[7:4] R_TEMP_OFFSET [3:0] R_TXDIS_POL[2] R_TXACT_POL[1] R_CLKALM_POL[0] R_DAC_TXACT[2:0] R_TXACT_THRU[0] R_DAC1[7:0] R_DAC2[7:0] R_DUTY[4:0] R_MODE[3:0] R_TEMP[6:0] AKM Test 00h 00h 01h 01h 01h 02h 04h 05h 06h 07h 08h 0Ch 0Dh 13h Oscillator Frequency Temperature sensor offset TXDIS Polarity TXACT Polarity CLKALM Polarity DAC(TXACT) TXACT Hold I-DAC1 Current Setting I-DAC2 Current Setting Duty Adjustment Operation Mode Status Detected Temperature Test for AKM (Reserved) Bit R/W (Note 1) 4 R/W 4 R/W 1 1 1 3 1 8 8 5 4 7 R/W R/W R/W R/W R/W R/W R/W R/W R R NA Remark
0: Shutdown at "H" 1: Shutdown at "L" 0: "H" at TXACT detection 1: "L" at TXACT detection 0: "H" at CLKALM detection 1: "L" at CLKALM detection see Table 3-2 0: TXACT Hold (Normal Operation) 1: TXACT (Real-Time) see Table 2-5 see Table 2-6 see Table 2-4 see Table 6-3 see Table 2-8 Reserved
Note 1: R: Read Only. R/W: Read/Write, Write data is hold unless re-writing or operation mode changing. All adjustment would be done by R/W registers. Table 5-7 Register Map Address D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh - 13h DAC1 DAC2 DUTY MODE
D6 D5 VREFTRIM
D4
D3
D2 D1 D0 TEMP_OFFSET TXDIS_ TXACT_ CLKALM_ POL POL POL DAC_TXACT TXACT_ THRU
TEMP Reserved (AKM Test)

-26-
2003/12
ASAHI KASEI 6. Operation Mode The AK2574 has 3 operating modes: Self-running, Adjustment and EEPROM mode.
[AK2574]
6.1 Self-running Mode Self-running mode is ready for normal operation after all adjustments are completed. In this mode, temperature detection, EEPROM access and feeding current are automatically performed using the on-chip oscillator. The AK2574 works in this mode after power-on. 6.2 Adjustment Mode Adjustment mode is designed for training the LD characteristics. The AK2574 operates according to the register settings set through the I2CTM I/F. 6.3 EEPROM Mode EEPROM mode is used for storing LD characteristics into EEPROM. Transition from EEPROM mode to Adjustment mode is prohibition. 6.4 MODE Control The AK2574 operation modes are changed through the I2CTM interface. Table 6-1 shows the access limitation of each operation mode and Table 6-2 shows the command to change operation mode. Note: The I2CTM interface access is prohibited for 2ms after power-on or mode transfer to self-running mode. Table 6-1 Access limitation of each operation mode EEPROM Access Operation mode Read Write Self-running mode x (WP="L") Adjustment mode x (WP="L") EEPROM mode (WP="L") WP = "H" x Self-running mode only (User Area Only) Table 6-2 Operation mode change Device Address R/W 1010100 W 1010100 W 1010100 W Address 11111111 11111111 11111111 Data 10100000 10100111 10101110 Register Access Write x (except mode-change command) x (except mode-change command) x
Read x
Operation mode Self-running mode Adjustment mode EEPROM mode
6.5 Operation Mode Protection When set WP = "H", only self-running mode is selected. 6.6 Operation Mode Status Operation mode is stored in R_MODE register. Table 6-3 shows the relationship between the Operation mode and R_MODE. When set WP = "H", access to R_MODE is prohibition. Table 6-3 R_MODE Operation mode Self-running mode Adjustment mode EEPROM mode R_MODE[3:0] 0000 0111 1110

-27-
2003/12
ASAHI KASEI 7. Module Adjustment Example Table 7-1 shows the module adjustment example.
[AK2574]
Table 7-1 Module Adjustment Example No. Item Contents 1 Go to Adjustment mode Issues "Changing to Adjustment mode command" (see Table 5-2) via I2CTM I/F. 2 Continuous operation Set BRST="H" to operate AK2574 as a continuous operation. 3 LD current adjustment Adjust R_DAC1 for modulation current and R_DAC2 for BIAS current of LD. 4 Duty adjustment Adjust R_DUTY for 50% duty of LD power, if necessary. After duty adjustment, tune MOD and BIAS current by R_DAC1 and R_DAC2, if necessary. 5 TXACT adjustment Adjust LD power by R_DAC1 and R_DAC2 to 3dB down of minimum LD power that you would like to detect TXACT. Input the burst control signal and adjust R_DAC_TXACT for tunning TXACT detection time. For more information, see "3.1 TXACT". 6 Verification of TXACT Set R_DAC1 and R_DAC2 back to normal power. Confirm TXACT detection time. 7 Read temperature data Read R_TEMP (on-chip temperature sensor detection temperature). 8 Estimate LD temperature (1) 2 or more temperature adjustment characteristics Do step 2 to 8 with different temperature and estimate LD current data of look-up table. (2) Single point adjustment Calculate LD current data of look-up table with on-chip temperature sensor gain (-1.49/LSB), R_TEMP and LD characteristics. Write adjustment data to (1) Make the data for EEPROM. EEPROM (2) Issue mode change command to EEPROM. (3) Write adjustment data to EEPROM. (4) Read EEPROM data and verify it. Self running mode Issue mode change command to self-running. AK2574 operates temperature detection, feed current in response to temperature, and a feedback operation automatically according to the data in EEPROM.
9
10

-28-
2003/12
ASAHI KASEI . Circuit Example Fig-A illustrates circuit example of AK2574. Fig-A Circuit Example
VCC = 3.3V +/- 0.2V C19 C20 C17 C18 LD R1 = 330 +/- 1% R2 = 12k +/- 1% R3 = 82k +/- 1% R5=R6=R7 = 4.7k10k R8 = 4.710 C1=C2=0.1uF +/- 50% (under operating temperature) C11=C13=C15=C17=C19=C21 = 0.1uF C12=C14=C16=C18=C20=C22 = 0.01uF or 0.001uF C16 C15
[AK2574]
PD
R8
C1 37 C2 R1 25 IMODN IMODN NC VSSBI IBIAS C1 NC PDIN R3 R2 TESTMON BIAS AVDD AVSS TXACT TEST1 CLKALM DVSS SDA SCL R5 VCC or GND DVDD NC C11 C12 DATAN IBIAS VSSBI IMOD VSSMD IMOD IBIAS NC
IBIASC2 IBIASR1
VSSMD
VDDMD VDDDR VSSDR TEST2 TEST3 TEST4 TEST5 BRSTP BRSTN DATAP CLKN TXDIS CLKP TEST6 NC NC SEL WP Open 13 R132 R134 R131 = R133 = 130 R132 = R134 = 82 R131 R133 LVPECL I/F C13 C14
AK2574VB
C21
C22
1
R6 Pull-up or pull down Do not leave open VCC or GND Normal Operation with Open: Pull-down Shutdown Operation with Open: Pull-up Do not leave open R7
LVPECL I/F (see below) For full access: GND For write protection: Open or VDD
LVPECL I/F
DATA Only R111 TD + R112 TD R124 R125 VDD or Open CLKP CLKN R111 = R113 = 130 R112 = R114 = 82 R127 CLK R128 CLK + R126 CLKP DATAP TD + R122 DATA & CLK R121 DATAP R123 DATAN SEL
R113 TD R114
DATAN SEL
CLKN
R121 = R123 = R125 = R127 = 130 R122 = R124 = R126 = R128 = 82

-29-
2003/12
ASAHI KASEI
[AK2574]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

-30-
2003/12

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